The present invention relates to a technique for manufacturing semiconductor integrated circuit devices, and more particularly to a technique effectively applied to the photolithography (hereinafter simply called a lithography) technique in the process of manufacturing semiconductor integrated circuit devices.
In the manufacturing of semiconductor integrated circuit devices (LSI: Large Scale Integrated circuit), the lithography technology has been used for forming micro-patterns on a semiconductor wafer (hereinafter simply called a wafer).
Techniques related to the lithography technology are described, for example, in Japanese Patent Laid-open No. 10-50788. This discloses a system that couples both an electronic system which has information available for determining regeneration, and a lithography processing apparatus by communications, and that automatically determines whether it is a failure or a pass on the basis of results of a tester, and that executes regenerative processing without delay. Importance underlying this system is that communication and information are connected to each other. In the electronic system, the electronic system may be separated from the lithography processing apparatus, or the electronic system information irrespective of whether respective apparatuses are separated, consistent or integrated. It is however assumed that the apparatuses should be integrated for convenience.
Besides, for example, there are also technologies disclosed in Japanese Patent Laid-open No. 11-109654 and No. 10-154664.
In a lithography step in the process of manufacturing semiconductor integrated circuit devices, however, there is a challenge for addressing how semiconductor integrated circuit devices should be efficiently manufactured in a short time and in high quality.
For example, in a plan of a line for processing a large-diameter wafer of approximately 300 mm, the present inventors considered a strategy of allocating a fixed processing time for each step and eliminating a stock between steps in the production on a very QTAT (Quick Turn Around Time) basis. For implementing this strategy, a work time must be consistent per lot on a line in a lithography step. The lithography, however, involves a predecessor work, development testing, regeneration work and the like, unlike other steps, thereby causing an unstable work time which could result in pulsatile material flows and increased TAT. It should be noted that the predecessor work refers to acquisition of a variety of information on the manufacturing by introducing a wafer for testing on a manufacturing line prior to the manufacturing of wafers for products.
The predecessor work, development testing and regeneration work can involve division and/or aggregation of lots, which however is quite difficult to accommodate with a strategy of relying on an automatic schedule control system to manage cassettes for closed containers which support a mini-environment that is a standard for a manufacturing line for the large-diameter wafers.
In the development testing and regeneration, lots are intensively supplied from a large number of aligners to a small number of apparatuses dedicated to the associated processing, causing an overload on conveyers and wasteful TAT losses due to conveyance, shifting, other handling, waiting therefor, and the like.
Further, since the aligner which supports a large-diameter wafer is very expensive, it is essential to increase the operating rate and throughput, however, the aforementioned predecessor work and regeneration processing largely reduce the operating rate of the aligner. On the other hand, since the large-diameter wafer provides the amount of produced chips per wafer increased by a factor of 2.25, a flexible production scheme and an ensured quality are essential. The flexible production causes a lower operating rate due to an increased predecessor frequency, as well as a significant reduction in the amount of data available for quality control due to a decreased amount of testing data on the same types of products, or difficulties in ensuring the quality due to an increased error depending on the type This results in an increased tendency to rely on the predecessor, development testing and regeneration. It is difficult to satisfy both conflicting requirements while increasingly severe accuracies are demanded for products.
While the lithography system disclosed in the aforementioned patent document could accomplish an adequately increased efficiency, if implemented, the present inventors have found that the disclosed system implies the following problems.
First, the lithography system determines pass/fail for wafers based on a test on a set number of extracted wafers, and proceeds to the regeneration if wafers are determined to fall out of criteria, where all wafers in a lot are subjected to the regeneration. In this case, when the regeneration frequency is increased due to strict conditions on the quality requirements or in a flexible production, the operating rate of associated apparatuses becomes lower, with a resulting increase in TAT.
Also, the consistency refers to the arrangement in a single direction conforming to a processing flow (processing, testing and regeneration), without consideration of the association with other processing such as those after the regeneration, predecessor, and the like, so that it cannot be said that the resulting effects and applicable range are sufficient. In addition, the removal of the resist is considered on the assumption that the resist is removed by an asher in a vacuum chamber. Therefore, a wafer cannot be looped back to repetitive processing immediately after a resist has been removed from the wafer, and continuation to post-processing cannot yet be realized.
Further, since the foregoing system is based on the concept of lot testing, it fails to integrate functions required for automation, such as a testing step prior to regeneration, investigation of causes for regeneration, and the like.
In view of the above problems inherent to the prior art, an object of the present invention is to provide a technology which is capable of improving the efficiency of a lithography step in a process of manufacturing semiconductor integrated circuit devices.
An object of the present invention is to provide a technology which is capable of reducing a period for a lithography step in a process of manufacturing semiconductor integrated circuit devices.
An object of the present invention is to provide a technique which is capable of improving the quality of semiconductor integrated circuit devices.
The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.
The following outlines a concept of a representative aspect of the invention disclosed in the present application.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit devices for each semiconductor wafer comprising a step of depositing a photosensitive organic film, a step of performing exposure processing, a step of performing development processing, a step of conducting a test, and a consistent processing step for removing the photosensitive organic film of a semiconductor determined as nonstandard in the test, and returning again to the step of depositing the photosensitive organic film to regenerate the semiconductor wafer, wherein during the regeneration processing for the semiconductor wafer, other processing is automatically performed in parallel for other semiconductor wafers of the plurality of semiconductor wafers in a system for performing the consistent processing.
According to another aspect of the present invention, there is provided the semiconductor integrated circuit devices, wherein the semiconductor wafer to be regenerated is processed during the processing after the regeneration, using the amount of correction used when the semiconductor wafer was processed and the amount of correction calculated from the result instead of the amount of correction used when other semiconductor wafers are processed.
According to still another aspect of the present invention, there is provided the semiconductor integrated circuit devices, wherein the step of specifying a waiting semiconductor wafer due to determination of a semiconductor wafer which should be regenerated, and waiting the semiconductor wafer is controlled to be able to specify a plurality of waiting semiconductor wafers.
According to still another aspect of the present invention, there is provided the semiconductor integrated circuit devices, wherein the tester has a cassette loader, and processes both of a semiconductor wafer supplied from a coater/developer connected in an in-line configuration, and a semiconductor wafer supplied from the cassette loader.
According to still another aspect of the present invention, there is provided the semiconductor integrated circuit devices, wherein the cassette loader of the tester is installed in the same direction or on the same plane as the cassette loader of the coater/developer, and has an interface with conveying means common to the cassette loader of the coater/developer.
According to still another aspect of the present invention, there is provided the semiconductor integrated circuit devices, wherein a plurality of testers are connected through a conveyer for conveying supplied semiconductor wafers within a system for performing the consistent processing to sequentially process these test in a pipeline operation.
According to still another aspect of the present invention, there is provided the semiconductor integrated circuit devices, wherein when a nonstandard failure is detected when the plurality of tests are sequentially processed in a pipeline operation, the test is detailed, and a subsequent test is conducted based on the previous test.